1. Field of the Invention
This invention relates to clock distribution in integrated circuits. In particular, this invention relates to providing a low skew clock signal using clock buffer circuits in sub-blocks of an integrated circuit.
2. The Background Art
In very large scale integrated circuits, every sub-block which constitutes the whole chip is synchronized to either the rising edge or the falling edge of a reference clock source. However, due to physical separation and differential loading of sub-blocks, transition edges may vary slightly between sub-blocks. This variation is called skew.
There are many techniques used to minimize skew. One clock distribution scheme, known as H-tree clock distribution, attempts to minimize skew by equalizing the distance between the origin of the clock signal and the various destination sub-blocks of the clock signal.
FIG. 1 is a schematic diagram showing an H-tree clock distribution scheme in accordance with the prior art. In the H-tree clock distribution scheme 10, a reference clock signal is applied at point 12. From point 12, the clock signal propagates to points 14 and 16. From point 14 the signal propagates to points 18 and 20, and from point 16 the signal propagates to points 22 and 24. Ideally, the clock signal reaches points 18, 20, 22 and 24 at the same time. If this is the case, then there is no skew.
The H-tree employs multiple layers, depending on the complexity of the chip. If another layer is desired, points 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54 and 56 should receive the clock signal simultaneously. In the next layer, points 58, 60, 62, 64 and all other similarly situated points (not shown) should also receive the clock signal simultaneously.
At the end points of the clock tree, the circuits receiving the clock signals may differ in their impedance, or loading. These loading differences result in differing propagation delays along the branches of the tree, and result in skew. To balance loading, dummy loads may be implanted at receiving points or, alternatively, end point driving circuit sizes may be trimmed.
Balancing loading using existing methods has disadvantages. If imbalances are large, dummy loads may require excessive silicon real estate. Also, changing the circuit size at one end point by adding dummy loads or trimming the circuit size results in changing the relative loading at other equivalent end points. Thus, all equivalent end points may then require adjustment. When there are many end points, adjusting the loading at all end points is non-trivial.
A clock buffer circuit is disclosed. The clock buffer circuit is included in each sub-block of a clock distribution structure in an integrated circuit. Each clock buffer circuit comprises a plurality of driving inverters, and each clock buffer circuit presents an equal input load to the previous driver, regardless of the amount of load in the sub-block circuit. In each sub-block, the clock buffer circuit is connected to provide an output including the combined signals of a portion of the inverters. The portion is approximated by the load of the circuit in the sub-block divided by the load of the circuit in the sub-block having the greatest load of any sub-block. The outputs of inverters not connected to the load of the sub-block circuit are wired to power and ground terminals. Each driving inverter may comprise a pMOS FET paired with an nMOS FET. A method for designing such a clock buffer circuit is also disclosed.